NDLI: CTC: An end-to-end flow control protocol for multi-core systems-on-chip

Content Provider	IEEE Xplore Digital Library
Author	Concer, N. Bononi, L. Soulie, M. Locatelli, R. Carloni, L.P.
Copyright Year	2009
Description	Author affiliation: ST Microelectronics, Grenoble, France (Soulie, M.; Locatelli, R.) \|\| Computer Science Department, Columbia University in the City of New York, USA (Carloni, L.P.) \|\| Dipartimento di Scienze dell'Informazione, Università di Bologna, Italy (Concer, N.; Bononi, L.)
Abstract	We propose Connection then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in networks-on-chip (NoC) for multicore systems-on-chip. CTC is based on the classic end-to-end credit-based flow control protocol but differs from it because it uses a network interface micro-architecture where a single credit counter and a single input data queue are shared among all possible communications. This architectural simplification reduces the area occupation of the network interfaces and increases their design reuse: for instance, the same network interface can be used to connect a core independently of the number of incoming and outgoing communications. CTC, however, requires a handshake preamble to initialize the credit counter in the sender network interface based on the buffering capacity of the receiver network interface. While this necessarily introduces a latency overhead in the transfer of a message, simulationbased experimental results show that the penalty in performance is limited when large messages need to be transferred, thus making CTC a valid solution for particular classes of applications such as video stream processing.
Starting Page	193
Ending Page	202
File Size	1185615
Page Count	10
File Format	PDF
ISBN	9781424441426
DOI	10.1109/NOCS.2009.5071467
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Multicore processing Network-on-a-chip Communication system control System recovery Streaming media Control systems Network interfaces Delay Counting circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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