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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Prado, B. Barros, E. Silva, L. Cabrai, A. Bruno, R. Demente, G. |
| Copyright Year | 2009 |
| Description | Author affiliation: Informatics Center, Federal University of Pemambuco, Recife, Brazil (Prado, B.; Barros, E.; Silva, L.; Cabrai, A.; Bruno, R.; Demente, G.) |
| Abstract | Due to the increasing complexity of modern electronic systems, functional verification is a really hard and crucial activity to ensure the quality of digital system design. During all design phases, the verification team must deal with conflicting metrics: quality, cost and time-to-market. In order to be able to deal with this scenario and constraints, it is mandatory an efficient verification methodology to release high quality components satisfying the project's budget and schedule. This work aims to propose a functional verification methodology that extends the considered state of art of verification methodologies (VeriSC and OVM) to support iterative and incremental development flows. The proposal includes architectural verification environment improvements and new techniques for functional coverage, which delivers an easy to implement but powerful functional coverage analysis. |
| Starting Page | 207 |
| Ending Page | 210 |
| File Size | 331465 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457702372 |
| e-ISBN | 9781457702365 |
| DOI | 10.1109/VLSISOC.2009.6041357 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-10-12 |
| Publisher Place | Brazil |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase change materials development flow Time varying systems cascade Time domain analysis digital system Field-flow fractionation iterative interoperability incremental verification methodology |
| Content Type | Text |
| Resource Type | Article |
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