NDLI: Challenges and emerging technologies for system integration beyound the end of the roadmap of nano-CMOS

Content Provider	IEEE Xplore Digital Library
Author	Bampi, S.
Copyright Year	2009
Description	Author affiliation: Universidade Federal do Rio Grande do Sul, Brazil (Bampi, S.)
Abstract	By 2020 it is very likely that nano-CMOS will reach the end of the scaling roadmap. Such end will not mean the demise of silicon technology at all. While there are uncertainties as to what will be the show stoppers, there is a large number of transitional and compatible to CMOS technologies that will be more important than just 2D scaling. This paper discusses possible limitations bringing the end of scaling and also proposes a likely scenario for hardware technology evolution and related challenges for integrating systems in the next 20 years. The scenario beyond the end of the roadmap is drawn, in which key technologies will be developed to be compatible with nano-scaled CMOS in silicon, and not to replace it entirely. Transitional technologies will rather coexist and be built upon a basic CMOS-like technology platform of silicon-on-insulator. Radically new devices at the 1 – 10 nm scale will most likely be built on a silicon substrate with the same technical requirements (such as cleanness, lithographic resolution, long range ordering, etc) of near end-of-roadmap CMOS industry. The end of scaling will not necessarily lead to the onset of a post-silicon era. Advanced materials research has not pointed so far to a non-silicon scenario well beyond 2020. The computing systems challenges will be dealt with new forms of integration, hierarchically ordered from the micron-level, to sub-micron level (500nm to 100nm) non-digital, down to nano-scaled transistors on silicon further down to 10 nm. In this hierarchy, at the bottom, it is highly possible that disruptive molecular level devices (self-assembled in the scale of 2 to 10 nanometers) will eventually be production-worthy for 100 Giga to Tera-scale devices integration. Structures like graphene-based carbon tubes or planes are the most viable candidates for molecular devices. In this presentation the computer systems relevant issues of systems power dissipation, noise, hardware design complexity, and resilience to systems failures in the presence of device variances and faults, are addressed as the challenging computing research topics that will guide future research in computing architectures at the tera-scale integration beyond 2020.
Starting Page	4
Ending Page	5
File Size	66891
Page Count	2
File Format	PDF
ISBN	9781457702372
e-ISBN	9781457702365
DOI	10.1109/VLSISOC.2009.6041321
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-12
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Synopsis

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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