NDLI: A 1.3µW $0.0075mm^{2}$ neural amplifier and capacitor-integrated electrodes for high density neural implant recording

Content Provider	IEEE Xplore Digital Library
Author	Elzeftawi, M. Beach, S. Wang, L. Theogarajan, L.
Copyright Year	2012
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Univ. of California Santa Barbara, Santa Barbara, CA, USA (Elzeftawi, M.; Beach, S.; Wang, L.; Theogarajan, L.)
Abstract	A key issue in the design of biomedical implants is the design of low-power area-efficient circuits that allow for high-density neural recording. This paper presents an ultra low-power (<;1.4μW), area efficient low-noise neural amplifier that utilizes current-feedback miller-compensation technique and occupies ~ $0.0075mm^{2}$ silicon area. Integrating the large input capacitor within the electrodes saves valuable silicon area. The amplified signal is digitized by a 10-bit sigma-delta ADC that is based on an area-efficient self-biased amplifier. The ADC consumes only 4.8μW from a 1.2V supply, when sampled with a 1.6MHz, and occupies $0.03mm^{2}$ chip area. The chip was fabricated in 0.13μm CMOS.
Sponsorship	Circuits & Syst. Soc.
Starting Page	236
Ending Page	239
File Size	2046770
Page Count	4
File Format	PDF
ISBN	9781467322911
e-ISBN	9781467322935
e-ISBN	9781467322928
DOI	10.1109/BioCAS.2012.6418453
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-28
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrodes Voltage measurement Sigma delta modulation Noise Capacitors Implants Noise measurement
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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