NDLI: A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES

Content Provider	IEEE Xplore Digital Library
Author	Fayed, M. El-Kharashi, M.W. Gebali, F.
Copyright Year	2006
Description	Author affiliation: Univ. of Victoria, Victoria (Fayed, M.)
Abstract	Nowadays, data encryption and decryption have become mandatory for any real-time communication applications. We propose a novel, area-speed efficient, high-speed architecture for the Advanced Encryption Standard hardware implementation. Our proposed architecture utilizes the composite field technique for SubBytes/InvSubBytes transformation instead of the traditionally-used look up table technique. As a result, the unbreakable delay of using look up tables in the traditional technique is eliminated. This, in turn, enables sub-pipelining implementation for further speeding up. Moreover, composite field arithmetic is employed to reduce the critical path delay. We propose a new algorithm to generate the optimum isomorphic mapping matrix, which reduces the critical path delay dramatically. In addition, an efficient key expansion architecture suitable for real-time applications is presented. Using the proposed architecture, a fully sub-pipelined implementation with 6 sub-stages in each round can achieve a throughput of 49.401 Gbps on a Xilinx XC2V6000FF1152-6 device in non-feedback mode, which is twice faster than the fastest Advanced Encryption Standard FPGA implementation known to date.
Starting Page	1
Ending Page	2
File Size	85702
Page Count	2
File Format	PDF
ISBN	0780397703
DOI	10.1109/ITICT.2006.358286
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-10
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Symmetric-key Cipher Data engineering Throughput Electronic mail Application software Delay Secret-key Cipher Block Cipher Computer architecture Composite Field Multiplicative Inverse in GF(28) Private Key Cipher Advanced Encryption Standard Hardware Cryptography Sub-pipelining Arithmetic
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES

Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining (2001)

An Area-Throughput Efficient FPGA Implementation of the Block Cipher AES Algorithm

High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip

FPGA implementation of fully pipelined Advanced Encryption Standard

Aes-128 bit algorithm using fully pipelined architecture for secret communication.

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

An approach to image compression with partial encryption without sharing the secret key (2012).

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA

A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES

Similar Documents

A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES

Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining (2001)

An Area-Throughput Efficient FPGA Implementation of the Block Cipher AES Algorithm

High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip

FPGA implementation of fully pipelined Advanced Encryption Standard

Aes-128 bit algorithm using fully pipelined architecture for secret communication.

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

An approach to image compression with partial encryption without sharing the secret key (2012).

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA

A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES