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Aes-128 bit algorithm using fully pipelined architecture for secret communication.
| Content Provider | CiteSeerX |
|---|---|
| Abstract | In this paper, an efficient method for high speed hardware implementation of AES algorithm is presented. So far, many implementations of AES have been proposed, for various goals that effect the Sub Byte transformation in various ways. These methods of implementation are based on combinational logic and are done in polynomial bases. In the proposed architecture, it is done by using composite field arithmetic in normal bases. In addition, efficient key expansion architecture suitable for 6 sub pipelined round units is also presented. These designs were described using VerilogHDL, simulated using Modelsim. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Aes-128 Bit Algorithm Using Fully Secret Communication Various Goal Combinational Logic High Speed Hardware Implementation Aes Algorithm Various Way Many Implementation Sub Byte Transformation Efficient Method Composite Field Normal Base Efficient Key Expansion Architecture Polynomial Base Proposed Architecture |
| Content Type | Text |
