NDLI: Runtime Control of Subthreshold Current using DoubleGate Device Technology

Content Provider	IEEE Xplore Digital Library
Author	Beckett, P. Rudolph, H.
Copyright Year	2010
Abstract	The close link between power and performance represents a significant hurdle to the design of portable embedded systems. As supply voltage falls, thereby saving dynamic power, the impact of threshold voltage on delay becomes greater so that it will become increasingly difficult to set a fixed threshold voltage that optimizes both performance and static power. This paper proposes a method around these conflicting requirements by allowing threshold voltages to be dynamically adjusted at run time via back–gate control on thin–body double–gate Silicon on Insulator (TBDGSOI) transistors. Using a multi–level simulation approach, with SPICE and VHDL-AMS, and using a small RISC microprocessor architecture as an example, it is shown that reductions in subthreshold leakage of between 6X and 11X can be achieved using this run-time control technique under a number of small software workloads.
Starting Page	245
Ending Page	249
File Size	689376
Page Count	5
File Format	PDF
ISBN	9780769539782
e-ISBN	9781424460267
DOI	10.1109/DELTA.2010.28
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-01-13
Publisher Place	Vietnam
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	modeling low power computer architecture VHDL-AMS SOI Voltage control Delay double gate Silicon on insulator technology Reduced instruction set computing Microprocessors Embedded system Computer architecture SPICE Threshold voltage Subthreshold current
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Multiple-gate silicon on insulator (SOI) MOSFETs: Device design and analysis

Uncriticality-Directed Low-Power Instruction Scheduling

Virtual Double-Gate Operation in Conventional SOI CMOS Technology

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)

Device and circuit considerations for high performance SOI technologies

Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs

Modified surface potential based current modeling of thin silicon channel double gate SOI FinFETs

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

Runtime Control of Subthreshold Current using DoubleGate Device Technology

Similar Documents

Multiple-gate silicon on insulator (SOI) MOSFETs: Device design and analysis

Uncriticality-Directed Low-Power Instruction Scheduling

Virtual Double-Gate Operation in Conventional SOI CMOS Technology

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)

Device and circuit considerations for high performance SOI technologies

Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs

Modified surface potential based current modeling of thin silicon channel double gate SOI FinFETs

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

Runtime Control of Subthreshold Current using DoubleGate Device Technology

Runtime Control of Subthreshold Current using DoubleGate Device Technology