NDLI: Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes

Content Provider	IEEE Xplore Digital Library
Author	Vladimirescu, A. Anghel, C. Amara, A. Gupta, N. Makosiej, A.
Copyright Year	2015
Description	Author affiliation: Lab. d'Electron. des Technol. de l'Inf., Commissariat a l'Energie Atomique et aux Energies Alternatives, Grenoble, France (Makosiej, A.) \|\| Inst. Super. d'Electron. de Paris ISEP, Paris, France (Vladimirescu, A.; Anghel, C.; Amara, A.; Gupta, N.)
Abstract	This paper describes the applicability of Tunnel FETs (TFET) to ultra-low-power sensor-node embedded Static Random-Access Memories (SRAM). Numerical TCAD device simulations were used first to characterize and optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its performance is analyzed. Our novel 8T TFET SRAM cell operates at $V_{dd}=1V$ or lower. The Read and Write Static Noise Margins (SNM) are evaluated at 120mV and 200mV, with the operation speed of 3.8GHz and 800MHz $V_{dd}=1V$ in read and write, respectively. The cell leakage is less than 5fA at $V_{dd}=1V.$ A sensor node architecture for implementation in a hybrid CMOS/TFET process with a large memory is proposed where the memory consumes as little as 2 fW/cell or 48 pW for a 4 kB array.
Starting Page	266
Ending Page	270
File Size	1314176
Page Count	5
File Format	PDF
ISBN	9781479989812
DOI	10.1109/IWASI.2015.7184974
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-18
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy-Delay Microprocessors Random access memory TFET Logic gates Capacitance CMOS integrated circuits Arrays Sensor Node Architecture SRAM Signal-to-Noise Margin (SNM)
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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