NDLI: An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

Content Provider	IEEE Xplore Digital Library
Author	Loukil, H. Kaanich, B. Masmoudi, N. Ben Atitallah, A. Kadionikp, P.
Copyright Year	2008
Description	Author affiliation: Lab. of Electron. & Inf. Technol., Sfax Nat. Eng. Sch., Sfax (Loukil, H.; Kaanich, B.; Masmoudi, N.) \|\| High Inst. of Electron. & Commun., Univ. of Sfax, Sfax (Ben Atitallah, A.) \|\| IMS Lab. - ENSEIRB, Univ. Bordeaux 1, Bordeaux (Kadionikp, P.)
Abstract	In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4times4 is composed by intra prediction 4times4, integer transform 4times4, quantization 4times4, inverse integer transform 4times4, inverse quantization 4times4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.
Starting Page	173
Ending Page	176
File Size	507856
Page Count	4
File Format	PDF
ISBN	9781424434794
DOI	10.1109/IDT.2008.4802491
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-20
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Video coding Quantization Parallel processing Throughput Hardware Automatic voltage control Videoconference Delay Pipeline processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Efficient Hardware Architecture Design for H.264/AVC INTRA 4X4 Algorithm

Hardware architecture for H.264/AVC deblocking filter algorithm

An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing

Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction

An H.264/AVC decoder with 4/spl times/4-block level pipeline

Hardware architecture design of an H.264/AVC video codec

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video

A Parallel and Pipelined Execution of H.264/AVC Intra Prediction

Hardware architecture for H.264/AVC INTRA 16×16 frame processing

An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

Similar Documents

An Efficient Hardware Architecture Design for H.264/AVC INTRA 4X4 Algorithm

Hardware architecture for H.264/AVC deblocking filter algorithm

An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing

Low latency and high throughput dedicated loop of transforms and quantization focusing in the H.264/AVC Intra Prediction

An H.264/AVC decoder with 4/spl times/4-block level pipeline

Hardware architecture design of an H.264/AVC video codec

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video

A Parallel and Pipelined Execution of H.264/AVC Intra Prediction

Hardware architecture for H.264/AVC INTRA 16×16 frame processing

An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm