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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Colesa, A. Tudoran, R. Banescu, S. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Comput. Sci., Tech. Univ. of Cluj-Napoca, Cluj-Napoca, Romania (Colesa, A.; Tudoran, R.; Banescu, S.) |
| Abstract | The paper presents a new software strategy for generating true random numbers, by creating several threads and letting them compete unsynchronized for a shared variable, whose value is read-modified-updated by each thread repeatedly. The generated sequence of random numbers consists of the final values of the shared variable. Our strategy is based on the functionality of the operating system's thread scheduler. Different values of the shared variable are obtained because the concurrent threads are preempted at different moments in their execution. We identified some software and hardware factors that make the scheduler generate context switches at unpredictable moments: execution environment, cache misses, the instruction execution pipeline and the imprecision of the hardware clock used to generate timer interrupts. We implemented the strategy on x86 architecture running Linux operating system. The random number sequences obtained pass over 90% of the NIST tests. |
| Starting Page | 439 |
| Ending Page | 444 |
| File Size | 258778 |
| Page Count | 6 |
| File Format | |
| ISBN | 9780769535234 |
| DOI | 10.1109/SYNASC.2008.36 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-09-26 |
| Publisher Place | Romania |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | software Pipelines Switches hardware clock Yarn URNG Linux Operating systems execution environment Computer architecture NIST Hardware random numbers race conditions Random number generation Clocks |
| Content Type | Text |
| Resource Type | Article |
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