NDLI: Multithread execution mechanisms on RICA-1 for massively parallel computation

Content Provider	IEEE Xplore Digital Library
Author	Okamato, K. Sakai, S. Matsuoka, H. Yokota, T. Hirono, H.
Copyright Year	1996
Description	Author affiliation: RWC Tsukuba Res. Center, Ibaraki, Japan (Okamato, K.)
Abstract	This paper presents a multithreaded processor architecture for massively parallel computers, and presents RICA-1 multithreaded processor based on it. RICA-1 provides fairly efficient mechanisms of message reception, thread invocation, message generation/transmission and synchronization. It provides simple communication pipelines. Computation pipelines and communication pipelines are highly fused within a processor architecture. Parallel primitives such as remote memory access, remote procedure call and synchronizations are efficiently performed by RICA-1. The first version of RICA-1 is being implemented by a CMOS standard cell chip with 200 K random gates and 13 KB internal RAMs. It is packed into the 527 pin CPGA package and will operate with a 50 MHz clock in August 1996. In RICA-1, communication pipelines and the RISC-type execution pipelines are highly fused by a simple sequencer and three sets of register files substantially reduces the thread switch overhead.
Starting Page	116
Ending Page	121
File Size	673832
Page Count	6
File Format	PDF
ISBN	0818676337
ISSN	1089795X
DOI	10.1109/PACT.1996.552653
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-20
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Computer architecture Yarn Synchronization Switches Concurrent computing Random access memory Packaging Clocks Communication switching
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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