NDLI: Random defect limited yield using a deterministic model

Content Provider	IEEE Xplore Digital Library
Author	Singh, A. Rosin, J.
Copyright Year	2001
Description	Author affiliation: Dominion Semicond. LLC, Manassas, VA, USA (Singh, A.)
Abstract	For success in the competitive semiconductor industry, the need to reduce cost per die is necessary. One way to accomplish this is to move to the next generation, or shrink technology to produce more die per wafer. Similarly, it is just as important to produce better die per wafer by minimizing the cycle time to detect and fix yield problems associated with the current technology. Wafer sort yield (good chips/wafer) can be broken into three components: random defect limited yield, systematic yield, and repeating yield loss. Random defect limited yield is due to defects, primarily caused by process equipment and their byproducts. Defects, usually randomly distributed, can also be localized to one or multiple die on a wafer. In-line QC inspection tools can detect most defects. Systematic yield losses are process-related and can affect all or some die on a wafer, or die by wafer region. Systematic yield losses are not detectable by in-line QC defect inspection tools. Repeating yield loss is due to reticle defects occurring on the same die within a reticle field. Repeating defects are caused by contamination on the stepper lens, by contamination of the pellicle that protects the reticle, or by reticle contamination. Reticle defects are sometimes detectable by in-line QC inspection tools. The paper focuses on calculations of random defect limited yield using a deterministic yield model. The model is used to prioritize defect problems and drive yield improvements. Actual examples are used to demonstrate the benefits and strengths of the deterministic model. We also discuss the methodology, assumptions, and limitations of this model.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	144
Ending Page	148
File Size	447785
Page Count	5
File Format	PDF
ISBN	0780366913
ISSN	07496877
DOI	10.1109/UGIM.2001.960317
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor process modeling Contamination Scanning electron microscopy Semiconductor device modeling Automatic optical inspection Optical sensors Optical microscopy Predictive models Circuits Electronics industry
Content Type	Text
Resource Type	Article

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