NDLI: A new learning approach to design fault tolerant ANNs: finally a zero HW-SW overhead

Content Provider	IEEE Xplore Digital Library
Author	Vargas, F. Lettnin, D. Brum, D. Prestes, D.
Copyright Year	2002
Description	Author affiliation: Electr. Eng. Dept., Catholic Univ., Porto Alegre, Brazil (Vargas, F.; Lettnin, D.; Brum, D.; Prestes, D.)
Abstract	We present a new approach to design fault tolerant artificial neural networks (ANNs). Additionally, this approach allows estimating the final network reliability. This approach is based on the mutation analysis technique and is used during the training process of the ANN. The basic idea is to train the ANN in the presence of faults (single-fault model is assumed). To do so, a set of faults is injected into the code describing the ANN. This procedure yields mutation versions of the original ANN code, which in turn are used to train the network in an iterative process with the designer until the moment when the ANN is no longer sensible to the single faults injected. In other words, the network became tolerant to the considered set of faults. A practical example where an ANN is used to recognize an electrocardiogram (ECG) and to measure ECG parameters illustrates the proposed methodology.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council (TTTC) Tech. Group on Dependable Comput. IEICE Special Interest Group on Syst. LSI Design Methodology IPS Japan
Starting Page	218
Ending Page	223
File Size	339000
Page Count	6
File Format	PDF
ISBN	0769518257
ISSN	10817735
DOI	10.1109/ATS.2002.1181714
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Artificial neural networks Genetic mutations Fault tolerant systems Electrocardiography Process design Biology computing Computer networks Intelligent systems Artificial intelligence
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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