NDLI: Non-scan design for testability based on fault oriented conflict analysis

Content Provider	IEEE Xplore Digital Library
Author	Dong Xiang Shan Gu Hideo Fujiwara
Copyright Year	2002
Description	Author affiliation: Inst. of Microelectron., Tsinghua Univ., Beijing, China (Dong Xiang; Shan Gu)
Abstract	A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. A new design for testability algorithm is proposed to select test points by using conflict+. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. Effective approximation schemes are adopted to get reasonable estimation of the testability measure. Several effective techniques are adopted to accelerate the process of the proposed design for testability algorithm.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council (TTTC) Tech. Group on Dependable Comput. IEICE Special Interest Group on Syst. LSI Design Methodology IPS Japan
Starting Page	86
Ending Page	91
File Size	1108647
Page Count	6
File Format	PDF
ISBN	0769518257
ISSN	10817735
DOI	10.1109/ATS.2002.1181691
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design for testability
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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