NDLI: SpeedGrade: an RTL path delay fault simulator

Content Provider	IEEE Xplore Digital Library
Author	Kee Sup Kim Jayabharathi, R. Carstens, C.
Copyright Year	2001
Description	Author affiliation: Test Technol., Intel Corp., Folsom, CA, USA (Kee Sup Kim)
Abstract	In the past, research on delay fault testing has been focused on test generation using various delay fault models on full scan gate level netlists. These tests are not very suitable for speed-binning since the confidence that the slowest paths have been covered is low. We have developed a novel methodology with an accompanying tool flow called SpeedGrade that performs path delay fault simulation using an RTL (Register Transfer Level) simulator. This novel method was used to translate the gate level path excitation conditions into higher level of abstraction without loss of accuracy. The higher efficiency of the RTL-based solution allowed for fault grading of functional patterns against the top critical paths in commercial microprocessor designs. The RTL-based approach also had the added benefit of being easier to use for debugging critical paths.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	239
Ending Page	243
File Size	440911
Page Count	5
File Format	PDF
ISBN	0769513786
ISSN	10817735
DOI	10.1109/ATS.2001.990289
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-19
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Microprocessors Propagation delay Failure analysis Production Cities and towns Debugging Process design Stress
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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