NDLI: Design of an optimal test access architecture using a genetic algorithm

Content Provider	IEEE Xplore Digital Library
Author	Ebadi, Z.S. Ivanov, A.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada (Ebadi, Z.S.)
Abstract	Test access is a major problem for core-based system-on-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. One of the most important issues in designing a test access architecture is testing time. Here, several issues related to the design of an optimal test access architecture with the goal of minimizing testing time are discussed. These issues include the assignment of cores to test buses, the distribution of test data width between multiple test buses, and the estimation of test data requirements to satisfy an upper bound on the testing time. Previous works show that all of these problems are NP-complete. Here, we applied a genetic algorithm (GA) to solve these problems. Experiments were run on two hypothetical but non-trivial SOCs using the implemented GA. The results show a 40% improvement. The performance improvement is principally due to our removing the constraints of the necessity of serialization and allowing the system to handle serial or parallel test data loading for any core.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	205
Ending Page	210
File Size	513704
Page Count	6
File Format	PDF
ISBN	0769513786
ISSN	10817735
DOI	10.1109/ATS.2001.990282
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-19
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Genetic algorithms System testing Computer architecture System-on-a-chip Upper bound Product development Manufacturing Concatenated codes Costs
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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