NDLI: Design validation of RTL circuits using evolutionary swarm intelligence

Content Provider	IEEE Xplore Digital Library
Author	Min Li Gent, K. Hsiao, M.S.
Copyright Year	2012
Description	Author affiliation: Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA (Min Li; Gent, K.; Hsiao, M.S.)
Abstract	In this paper, we present BEACON, a Branch-oriented Evolutionary Ant Colony OptimizatioN method which is a bio-inspired meta-heuristic for design validation and functional test generation. BEACON combines an evolutionary search technique with Ant Colony Optimization (ACO) for improved search capability. BEACON first cross-compiles the Verilog circuit source to a C++ base for fast simulation. Then, it profiles the code, keeping track of each branch and the number of times it has been visited in a database. Branch coverage provides a very useful metric for exploring the design, especially visiting the most critical states, including corner states, in the design. At 100% branch coverage, we can conclude that every control state described in the RTL has been visited. Thus, during execution, BEACON trims highly visited branches from the search and focuses the search on rarely occurring branches and paths. This approach gives a significant performance boost while maintaining a high level of coverage. Experimental results show that BEACON is able to achieve very high branch coverages with a fraction of computational cost. In addition, previous hard-to-reach corner states in the ITC99 benchmarks have now been reached by BEACON. New states can also be discovered from the RTL descriptions. For many circuits, one to two orders of magnitude speedups over existing methods have been achieved.
Starting Page	1
Ending Page	8
File Size	247802
Page Count	8
File Format	PDF
ISBN	9781467315944
ISSN	10893539
e-ISBN	9781467315951
DOI	10.1109/TEST.2012.6401556
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vectors Instruments Hardware design languages Databases Benchmark testing Measurement Sociology
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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