NDLI: On-chip diagnosis for early-life and wear-out failures

Content Provider	IEEE Xplore Digital Library
Author	Beckler, M. Blanton, R.D.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Beckler, M.; Blanton, R.D.)
Abstract	One approach for achieving integrated-system robustness centers on performing test during runtime, identifying the location of any faults (or potential faults), and repairing or avoiding the affected portion of the system. Fault dictionaries can be used to locate faults but conventional approaches require significant memory storage and are therefore limited to simplistic fault types. To overcome these limitations, three contributions are made that include: (i) enhancement of an unspecified transition fault model (called here the transition-X fault model, or TRAX for short) for capturing the misbehaviors expected from scaled technologies, (ii) development of a new type of hierarchical dictionary that only localizes to the level of repair or fault avoidance, and (iii) the design of a scalable architecture for retrieving and using the hierarchical dictionary for performing on-chip diagnosis. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate that early-life and wear-out failures can be accurately diagnosed with minimum overhead using TRAX dictionaries that are up to 2600x smaller than full-response dictionaries.
Sponsorship	IEEE
Starting Page	1
Ending Page	10
File Size	481616
Page Count	10
File Format	PDF
ISBN	9781467315944
ISSN	10893539
e-ISBN	9781467315951
DOI	10.1109/TEST.2012.6401580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Dictionaries System-on-a-chip Integrated circuit modeling Delay Maintenance engineering Robustness
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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