Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yuanyuan Cui Mian Lou Jianqing Xiao Xunying Zhang Senmao Shi Pengwei Lu |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. Grad., Xi'an Microelectron. Technol. Inst., Xi'an, China (Yuanyuan Cui; Mian Lou; Jianqing Xiao; Xunying Zhang; Senmao Shi; Pengwei Lu) |
| Abstract | For the space application, error detection and correction (EDAC) technique is often adopted to protect memory cells against Single Event Upset (SEU) errors. To improve the EDAC ability and in view of the parity memory having 8 bits width, a single error correction and double error detection (SEC-DED) (40,32) Hamming code is proposed. This scheme is on the base of (39,32) Hsiao code, adding a check bit to minimize the probability of 3 bits faults corrected in error. To optimize the EDAC circuit area, an algorithm solving mutual expressions is proposed. Experimental results indicate that, compared with the (39,32) Hsiao code method, the critical path delay of the encoder and that of the decoder are not increased, the EDAC circuit area only adds 297.044982 $um^{2},$ and if the 2GB external memory is protected by the two schemes respectively, the SEU failure rate using the (40,32) Hamming code method can be lower by one order of magnitude. By using the proposed algorithm solving mutual expressions, the circuit area of the encoder and decoder of the (40,32) Hamming code scheme all reduce 72.988199 $um^{2},$ and the encoder area decreases by 5.9%. |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 493397 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479928255 |
| ISSN | 21593450 |
| e-ISBN | 9781479928279 |
| DOI | 10.1109/TENCON.2013.6718953 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-22 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Decoding Circuit faults Vectors Delays Single event upsets Linear matrix inequalities Equations failure rate error detection and correction code Single Event Upset encoder decoder |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Computer Science Applications |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|