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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hoon Heo Jung-yong Lee Kwang-yeob Lee Chan-ho Lee |
| Copyright Year | 2013 |
| Description | Author affiliation: Sch. of Electron. Eng., Soongsil Univ., Seoul, South Korea (Chan-ho Lee) || Dept. of Comput. Eng., Seokyeong Univ., Seoul, South Korea (Hoon Heo; Jung-yong Lee; Kwang-yeob Lee) |
| Abstract | In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 641573 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479928255 |
| ISSN | 21593450 |
| e-ISBN | 9781479928279 |
| DOI | 10.1109/TENCON.2013.6718842 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-22 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Computer vision Registers System-on-chip Feature extraction Random access memory Object recognition Hamming Distance FAST BRIEF |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Computer Science Applications |
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