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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yin-Tsung Hwang Ying-Ji Chen Wei-Da Chen |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Chung-Hsing Univ. Taichung, Taichung (Yin-Tsung Hwang) |
| Abstract | In this paper, we propose a novel scalable FFT processor design capable of handling various transform sizes and data channels for multi-standard MIMO processing. The basic building blocks are split-radix 2/4/8 FFT modules in a modified MDC (multi-path delay commutator) form, pre- ordering data buffer, radix-2 butterfly module and twiddle factor module. Via proper data flow reconfiguration plus two alternative working frequencies, the processor can support 64, 128, 512, 1024-point transforms plus 1 to 4 MIMO channels. The hardware utilization is kept as 100% under various working modes. The implementation results in TSMC 0.18 um process indicate the design has a core size of about 5.5 $mm^{2},$ and a power consumption of 320 mW at 100 MHz. The delivered performance qualifies the proposed design for 802.1 In and 802.16e applications. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 237213 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424412716 |
| DOI | 10.1109/TENCON.2007.4429110 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-30 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Kernel MIMO OFDM Hardware Process design Delay Computer architecture Scalability Wireless communication Energy consumption |
| Content Type | Text |
| Resource Type | Article |
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