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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lu Xin Liang Yongsheng Xu Jun |
| Copyright Year | 2007 |
| Description | Author affiliation: Inst. of Inf. Technol., Shenzhen (Lu Xin; Liang Yongsheng) |
| Abstract | This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. The m-to-2m decoder has been introduced to generate more efficient new hardware implementations of check node update, which can obviously reduce the number of multiplication operations for normalized min-sum algorithm for high rate LDPC codes. Simulations have claimed the performance of normalized min-sum is nearly the same as that of Log-BP, namely the optimal algorithm. In general, this paper has proved that normalized min-sum is good choices as LDPC decoding methods. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 286502 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424412716 |
| DOI | 10.1109/TENCON.2007.4429021 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-30 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parity check codes AWGN Hardware Gaussian channels Turbo codes Iterative decoding Information technology Baseband Additive white noise Code standards |
| Content Type | Text |
| Resource Type | Article |
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