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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Weng Jun-Hong Jing-Shing Wen Ching-Yuan Yang |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Chung Hsing Univ., Taichung (Weng Jun-Hong; Jing-Shing Wen; Ching-Yuan Yang) |
| Abstract | A high-speed direct digital frequency synthesizer (DDFS) based on segmented digital-to-analog converter (DAC) is presented. In this work, a new approach to convert the digital phase information into sine amplitude is proposed such that high speed DDFS can be achieved. The DDFS has 10 bits of phase resolution and is implemented in 0.18 um CMOS technology with the die area 1.7 mm x 1.6 mm and the power consumption is about 271 mW. The simulated result of operation speed is up to 1 GHz and has spurious free dynamic range (SFDR) better than 55 dBc at low synthesized frequencies. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 516327 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424412716 |
| DOI | 10.1109/TENCON.2007.4429034 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-30 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency synthesizers Read only memory CMOS technology Energy consumption Table lookup Low pass filters Delay effects Digital-analog conversion Dynamic range Wireless communication |
| Content Type | Text |
| Resource Type | Article |
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