NDLI: The Implementation and Analysis of a New Self-sampling P1 Control All Digital Phase-locked Loop

Content Provider	IEEE Xplore Digital Library
Author	Chunyu Zhang Yabin Li Heming Li
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., North China Electr. Power Univ., Baoding (Chunyu Zhang; Yabin Li; Heming Li)
Abstract	A self-sampling PI (proportional-integral) control all digital phase-locked loop (ADPLL) is introduced in this paper. Our design is based on the self-sampling PI control scheme. An advantage of this is that the transfer function as linear approximation of the system model remains almost the same at different lock point, a feature enabling theoretical analysis and systematic design. The complete design procedure developed with field programmable gate array (FPGA) devices and the detailed theoretical analyses are presented. Static, dynamic results of simulation and experiments are also presented, which show and verify that this ADPLL has good behaviors over wide tracking speed, excellent stability and flexible control characteristics. The ADPLL can act as a key part or a key module in a system on chip (SoC) digital system to simply the entire system's hardware architecture and ensure the high system reliability
Starting Page	1
Ending Page	4
File Size	4221932
Page Count	4
File Format	PDF
ISBN	1424405483
DOI	10.1109/TENCON.2006.343702
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-14
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital control Phase locked loops Pi control Field programmable gate arrays Proportional control Transfer functions Linear approximation Stability System-on-a-chip Digital systems
Content Type	Text
Resource Type	Article

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