NDLI: An FPGA-Based Linear All-Digital Phase-Locked Loop

Content Provider	IEEE Xplore Digital Library
Author	Kumm, M. Klingbeil, H. Zipf, P.
Copyright Year	2004
Abstract	In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator is given.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2487
Ending Page	2497
Page Count	11
File Size	561205
File Format	PDF
ISSN	15498328
Volume Number	57
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Frequency Phased arrays Phase detection Field programmable analog arrays Field programmable gate arrays Detectors Oscillators Digital filters Analog-digital conversion PLL All-digital phase-locked loop (ADPLL) direct digital synthesizer (DDS) field-programmable gate array (FPGA)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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