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2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design

Table of contents

Technical Program

Hotel Information

Program Disturb Phenomenon by DIBL in MLC NAND Flash Device

Characterization of Low Frequency Noise in Floating Gate NAND Flash Memory

Optimization of Al2O3 Interpoly Dielectric for Embedded Flash Memory Applications

Advantage of Floating Gate B4-Flash over Retention Reliability after Cycling - Characterization by Variation of Transconductance

3-D Channel Structure Flash Having Short Channel Effect Immunity and Low Random Telegraph Signal Noise

Opportunities and Challenges in Multi-Times-Programmable Floating-Gate Logic Non-Volatile Memories

2T-FN eNVM with 90 nm Logic Process for Smart Card

A 90nm Embedded Page Flash for EEPROM Replacement in System On Chip

In-Ga-O Based Double-Heater Phase Change Memory Cell

Evidence of the Prominent Role of the Time-Under-Melt Parameter in the Reset Switching of Phase-Change Line Cells

Numerical Implementation of Low Field Resistance Drift for Phase Change Memory Simulations

Scaling Properties of Doped Sb2Te Phase Change Line Cells

A Novel Programming Method to Refresh a Long-Cycled Phase Change Memory Cell

Set of Electrical Characteristic Parameters Suitable for Reliability Analysis of Multimegabit Phase Change Memory Arrays

Improvement of Endurance and Switching Stability of Forming-Free CuxO RRAM

TMR Design Methodology for SPin-Transfer Torque RAM (SPRAM) with Nonvolatile and SRAM Compatible Operations

Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

On the Influence of Fin Corner Rounding in 3D Nanocrystal Flash Memories

Integration of Silicon Nanocrystal Memory Arrays with HfAlOx Based Interpoly Dielectric

On the Influence of Molecular Linker on Charge Transfer Rate in Hybrid Molecular (Ferrocene)/Silicon Field Effect Memories

Low Voltage and Fast Program and Erase SONOS with Thick Tunnel Oxide for Low Cost Embedded EEPROM-like Memory Applications

N-Channel Complementary Pairing in Nitride Trap Memory

A Highly Reliable Logic NVM "eCFlash (Embedded CMOS Flash)" Utilizing Differential Sense-Latch Cell with Charge-Trapping Storage

A 15ns 4Mb NVSRAM in 0.13u SONOS Technology

Influence and Comparison of Cu and Alu Metallization Schemes on Endurance of Embedded Flash Memories

C-Flash: An Ultra-Low Power Single Poly Logic NVM

Improved Retention for a Al2O3 IPD Embedded Flash Cell without Top-Oxide

A 65nm 1Mb SRAM Macro with Dynamic Voltage Scaling in Dual Power Supply Scheme for Low Power SoCs

An Oxide-Buffered BE-MANOS Charge-Trapping Device and the Role of Al2O3

Highly Scalable Fe(Ferroelectric)-NAND Cell with MFIS(Metal-Ferroelectric-Insulator-Semiconductor) Structure for Sub-10nm Tera-Bit Capacity NAND Flash Memories

Performance Enhancement in Ultra-Scaled SONOS FinFlash by Inclusion of High-k Dielectric in the Gate Stack

Numerical Simulation of Programming Transient Behavior in Charge Trapping Storage Memory

A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si)NAND Flash Memory with Rounded Corner (RC) Structure

Study of Charge Trapping Vertical Location and Capture Efficiency of SONOS-Type Devices by Gate-Sensing and Channel-Sensing (GSCS) Method

Anomalous Erase Behavior in Charge Trapping Memory Cells

The Impact of Interference on Multi-Level-Cell Applications in Scaled Nitride-Storage Flash Memory

Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer

Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory

Nitride Thickness Scaling Limitations in TANOS Charge Trapping Devices

2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop

2006 21st IEEE Non-Volatile Semiconductor Memory Workshop

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