NDLI: Experience in Virtual Testing of RSD cyclic A/D converters

Content Provider	IEEE Xplore Digital Library
Author	Kubar, M. Subrt, O. Martinek, P. Jakovenko, J.
Copyright Year	2009
Description	Author affiliation: Faculty of Electrical Engineering, Czech Technical University in Prague, Czech Republic (Martinek, P.; Jakovenko, J.) \|\| ASICentrum, Prague, Czech Republic (Kubar, M.; Subrt, O.)
Abstract	This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.
Starting Page	178
Ending Page	181
File Size	434344
Page Count	4
File Format	PDF
ISBN	9781424433414
DOI	10.1109/DDECS.2009.5012123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-15
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Hardware design languages Acceleration Integrated circuit testing Digital integrated circuits Logic Histograms Integrated circuit synthesis Iterative algorithms Feedback loop DNL Servo-Loop method Verilog-A Cyclic RSD A/D converter Virtual ADC Testing INL
Content Type	Text
Resource Type	Article

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