NDLI: Measurement of power supply noise tolerance of self-timed processor

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Measurement of power supply noise tolerance of self-timed processor

Content Provider	IEEE Xplore Digital Library
Author	Asada, K. Sogabe, T. Nakura, T. Ikeda, M.
Copyright Year	2009
Description	Author affiliation: Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan (Asada, K.; Sogabe, T.; Ikeda, M.) \|\| VLSI Design and Education Center (VDEC), 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan (Nakura, T.)
Abstract	We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18µm CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.
Starting Page	128
Ending Page	131
File Size	383405
Page Count	4
File Format	PDF
ISBN	9781424433414
DOI	10.1109/DDECS.2009.5012112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-15
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power measurement Noise measurement Power supplies Circuit noise CMOS process Process design CMOS logic circuits Logic design Logic circuits Error analysis
Content Type	Text
Resource Type	Article

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