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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhang Yu Wang Guang Yi Yao Su Ying |
| Copyright Year | 2010 |
| Description | Author affiliation: ASIC Design Center, School of Electronic and Information Engineering, Tian jin University, China, 300072 (Yao Su Ying) || School of Electronic and Information, Hang zhou Dianzi University, Zhejiang, China, 310018 (Zhang Yu; Wang Guang Yi) |
| Abstract | The image pipeline play a key role in improving the quality of color video image from the cmos/ccd image sensor in video surveillance system. The proposed pipeline is composed of automatic white balance, CFA color interpolation and illumination reducing. The automatic white balance module can reduce the color cast of one image which is undercoloured. By calculating the direction of centered pixel, the CFA color interpolation module can make the edge of one image more clearly. The illumination reducing module adjusts the brightness adaptively by setting up the non-linear mapping function. This pipeline has been implemented on Altera's FPGA EP1C12Q240C8. The experimental results show that the proposed image pipeline can obtain high PSNR value and be free from different illuminants. It can be good candidate for VLSI implementation. |
| Starting Page | 1988 |
| Ending Page | 1991 |
| File Size | 345491 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450459 |
| e-ISBN | 9781424450466 |
| DOI | 10.1109/ICIEA.2010.5515581 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-15 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pipelines Video surveillance Interpolation Lighting CMOS image sensors Charge-coupled image sensors Pixel Brightness Field programmable gate arrays PSNR digital image processing image pipeline CMOS/CCD image sensor |
| Content Type | Text |
| Resource Type | Article |
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