NDLI: Impact of NoFPGA IP router architecture on link bandwidth

Content Provider	IEEE Xplore Digital Library
Author	Alaraje, N. Hembroff, G.
Copyright Year	2008
Description	Author affiliation: Sch. of Technol., Michigan Technol. Univ., Houghton, MI (Alaraje, N.; Hembroff, G.)
Abstract	In todaypsilas world of advanced technology numerous applications are computationally intensive. This created an opportunity for the development of new system-on-chip (SoC) design techniques to allow easy IP cores (intellectual property cores) re-use and integration under time-to-market pressure. A wide range of these newly emerging design platforms is now drifting towards highly integrated system-on-chip designs with many on-chip processing resources like processors, DSPs, and memories. Using this technique, designers can build system-on-chip (SoC) by integrating dozens of IP cores. As the number of IP cores integrated on a chip increases, the on-chip communication and physical interconnections become a bottleneck. New system-on-chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA (network-on-FPGA), for future SoFPGA (system-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoFGPA design methodology built in a single FPGA device are addressed. Mainly, the performance analysis of the IPRouter of both torus and mesh topologies is addressed.
Starting Page	254
Ending Page	257
File Size	98874
Page Count	4
File Format	PDF
ISBN	9781424420292
DOI	10.1109/EIT.2008.4554308
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth System-on-a-chip Computer architecture Computer applications Intellectual property Time to market Digital signal processing chips Design methodology Field programmable gate arrays Performance analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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