NDLI: On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering

Content Provider	IEEE Xplore Digital Library
Author	Hanqing Xing Degang Chen Geiger, R.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA (Hanqing Xing; Degang Chen; Geiger, R.)
Abstract	On-chip testing of high-resolution high-speed DACs is extremely challenging because of the stringent requirements on the accuracy, speed and cost of the measurement circuits. This work proposed a new on-chip strategy for DAC linearity testing applying the proposed deterministic dynamic element matching (DDEM) technique. Low-accuracy two-step flash ADCs are used as test devices. Speed advantage of flash structure enables at-speed testing, while its accuracy and resolution are improved by DDEM algorithm, the second stage and dithering. In this paper, the architecture of the DDEM flash ADC and DDEM algorithm are described. The design consideration of the major circuit blocks are talked about. The test performance is analyzed theoretically and verified by simulation. Simulation shows that a dithering incorporated two-step flash DDEM ADC, which consists of a 6-bit coarse DDEM stage, a 6-bit fine stage and a 5-bit dithering DAC, with linearity of all the blocks only at about 6-bit level, is capable of testing 14-bit DACs.
Starting Page	117
Ending Page	122
File Size	216488
Page Count	6
File Format	PDF
ISBN	9781424420292
DOI	10.1109/EIT.2008.4554278
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linearity Circuit testing Built-in self-test Costs Circuit simulation Digital-analog conversion Velocity measurement Signal processing algorithms Manufacturing Automatic testing DDEM On-chip BIST DAC linearity
Content Type	Text
Resource Type	Article

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