NDLI: A novel architecture of a re-configurable parallel DSP processor

Content Provider	IEEE Xplore Digital Library
Author	Sinha, P. Sinha, A. Basu, D.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Windsor Univ., Ont., Canada (Sinha, P.)
Abstract	High performance, flexibility and low power consumption are the most important issues in the current DSP architectures. While the fastest programmable DSP processors are unable to meet the speed requirements of many advanced signal/image processing applications, the ASICS are not always suitable because of their inflexibility. Recently, dynamically re-configurable FPGAs have emerged as high performance flexible programmable hardware to execute highly parallel, computationally intensive functions of image and signal processing applications. However, since the FPGAs are not optimised for any particular application, they can not offer highest possible performance at lowest silicon cost for a given signal processing application. This paper addresses these issues by introducing a novel re-conflgurable parallel DSP processor which eliminates the drawbacks of the FPGAs and ASICs and offers a balance between flexibility, reconfiguration latency and performance.
Starting Page	71
Ending Page	74
File Size	349649
Page Count	4
File Format	PDF
ISBN	0780389344
DOI	10.1109/NEWCAS.2005.1496709
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Signal processing Field programmable gate arrays Energy consumption Computer architecture Image processing Application specific integrated circuits Hardware Concurrent computing High performance computing
Content Type	Text
Resource Type	Article

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