NDLI: Cache coherence support in a split-transaction bus for prototyping of system-on-chip multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Reed, J. Manjikian, N.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Queen's Univ., Kingsotn, Ont., Canada (Reed, J.; Manjikian, N.)
Abstract	This paper describes the implementation of a split-transaction bus with cache coherence support for use in prototyping of system-on-chip multiprocessors. The bus provides fair arbitration for separate address and data lines. The bus interface for each device on the bus includes a table for tracking all outstanding requests in order to match responses to requests and also to prevent coherence conflicts between requests from different sources. Coherence is also maintained for writeback buffers associated with each processor. A memory inhibit signal is used to enforce coherence when a request matches a modified cache block in a processor cache or writeback buffer. A VHDL implementation for logic simulation is used to verify the functionality of the bus with multiple processors and memory units, leading to synthesis for rapid prototyping in programmable logic.
Starting Page	273
Ending Page	276
File Size	355725
Page Count	4
File Format	PDF
ISBN	0780383222
DOI	10.1109/NEWCAS.2004.1359084
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes System-on-a-chip Logic Signal processing Signal synthesis Virtual prototyping Microelectronics Monitoring Delay Libraries
Content Type	Text
Resource Type	Article

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