NDLI: A network processor for a learning based routing protocol

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The 2nd Annual IEEE Northeast Workshop on Circuits and Systems (IEEE Cat. No.04EX799)

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Acknowledgments

Technical Program Committee

Table of content

An investigation into transistor-based adiabatic logic styles

A sub-1 volt CMOS bandgap voltage reference based on body-driven technique

A novel fully integrated floating-gate MOSFET radiation dosimeter using V/sub TH/ extractor

Technology portable delay model for DSM CMOS inverters

A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies

An FPGA-based wideband PLL without significant quantization noise

High-speed Viterbi decoder for W-LAN and broadband applications

A time-domain current model for fully CMOS logic gates

Passive macromodeling and sensitivity analysis of multiconductor transmission lines

New VLSI design of a max-log-MAP decoder

Optimizing architecture activity and logic depth for static and dynamic power reduction

Trends in low-voltage embedded RAMs

Ultra-low-voltage robust design issues in deep-submicron CMOS

Effects of packaging parasitics on high speed operation of VCSELs

SynAbs: model reduction tool for Verilog verification

Formal verification of a bus structure modeled in SystemC

Distributed control in testable high-level synthesis with low area and power overhead

An incremental approach for test scheduling and synthesis using genetic algorithms

An efficient methodology for design and verification of an equalizer for a software defined radio

DEI as a performance and defect analysis tool - dynamic electroluminescence imaging (DEI) from both sides of an EPROM memory device

Automatic synthesis from high level ASM to VHDL: a case study

Prototyping a hierarchical ring interconnect for system-on-chip multiprocessor implementations

A practical SOC simulation verification solution: robust design and automatic modeling

A comparison of time-domain and harmonic balance steady-state analyses for coupled device and circuit simulation

Speech recognition for game control

A technology portable analytical model for DSM CMOS inverter short-circuit power estimation

Multi-antenna WCDMA receiver design with CORDIC

Q-factor estimation of fabricated MEMS parallel-plate variable capacitors in MUMPs

A portable multi-band optoelectronic system for identifying and measuring the concentration of fluorophore substances

A novel evolutionary algorithm for analog VLSI layout placement design

Design of an autonomous biomicrorobot

Performance of probabilistic approaches to Steiner tree problem

Statistically partitioned, low power TCAM

Audio dynamic range compression characteristics based on an interpolating polynomial

Simulation of ring oscillators using the harmonic balance method

Haar wavelet decomposition of EEG signal for ocular artifact de-noising: a mathematical analysis

A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications

Power-aware pipelining design of an 8-bit CLA using PLA-styled all-N-transistor logic

Low-energy design of a 3G-compliant turbo decoder

A worst-case circuit delay verification technique considering power grid voltage variations

An efficient, low-complexity, normalized LMS algorithm for echo cancellation

Frequency domain filter using an accurate reconfigurable FFT/IFFT core

On-chip signaling for ultra low-voltage 0.13 /spl mu/m CMOS SOI technology

An adaptive DFE using an IIR feedback equalizer for 100Base-TX Ethernet

An embedded DRAM for MDLNS FIR filter

On-chip current sensing technique for hysteresis current controlled dc-dc converter

Clock recovery and data recovery design for LVDS transceiver used in LCD panels

Versatile input and output port circuit with power mode control signal

Asynchronous ADC/microprocessor interface

Synchronous to asynchronous conversion using GasP control

A novel technique to enhance the open loop gain of CMOS folded cascode OTA

A novel asynchronous wrapper using 1-of-4 data encoding and single-track handshaking

Design guidelines for leakage control transistor

On low power shift register hardware realizations for convolutional encoders and decoders

Speed and area trade-offs for FPGA-based implementation of RSA architectures

A novel pulsewidth control loop for high-speed circuit applications

The effect of power supply noise on ring oscillator phase noise

A 0.18 /spl mu/M CMOS fully differential transimpedance amplifier for optical receiver

Gain boosted amplifier design for low power-high speed applications

A high speed 512-bit modular multiplier for a RSA chip

A low power multi-standard sigma-delta ADC for WCDMA/GSM/Bluetooth applications

Low voltage high-SNR pipeline data converters

Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter

A new architecture for area and power efficient, high conversion rate successive approximation ADCs

A 3D bus interconnect for network line cards

A network processor for a learning based routing protocol

Efficient associative SIMD processing for non-tabular structured data

Design constraints of a hypertransport-compatible network-on-chip

Cache coherence support in a split-transaction bus for prototyping of system-on-chip multiprocessors

The frequency generation unit: a complex frequency synthesizer for multi-standard smart objects

A precision CMOS analog cubing circuit

Oversampled biorthogonal cosine-modulated filter bank realization using a critically constrained lifting scheme

A programmable CMOS RF frequency synthesizer for multi-standard wireless applications

A novel gain boosting technique for design of low power narrow-band RFCMOS LNAs

A bandgap reference circuit utilizing switching to reduce offsets and a novel technique for leakage current compensation

Analysis of metrics used to compare analog-to-digital converters

Leap-frog-based synthesis of CMOS micropower nth-order log-domain filters

Circuit simulation of S-parameter based interconnects via passive macromodels

New active realizations of floating lossless inductance and R-L impedance simulators

High voltage charge pump using standard CMOS technology

Robust design of a dynamically controlled low-power level-up shifter operating up to 300 V

All-pass building blocks realized with single negative type current conveyor

Characterization of stress induced defects in deep sub-micron MOSFETS

An algorithm for the automatic design and the power optimisation of active-G/sub m/-RC continuous-time biquadratic cells

Design of reconfigurable general finite field multiplier in GF (2/sup m/)

A user-configurable framework for testing prototype system-on-chip implementations

Towards software model checking using MDGs

Built-in self-test design of motion estimation computing array

A 0.85 V tunable gain 5 GHz cascode low noise amplifier

A fully-integrated CMOS RF front-end for Wi-Fi and Bluetooth

Shunt-peaking of MCML gates using active inductors

A reconfigurable RF power amplifier biasing scheme

An integrated inductorless quadrature voltage controlled oscillator design in a 47 GHz SiGe process

A fast adaptive heuristic for FPGA placement

Low-overhead asynchronous RISC microprocessor - a design experiment

A tool for automatic watermarking of IP designs

Carry free, bit parallel approximate squarers with linear complexity and constant delay

Pipeline-level control of self-resetting stage pipelines

PRMC: a multicontext FPGA with partially reconfigurable logic planes

[Inside back cover - blank]

NEWCAS 2004 [Back Cover]

A network processor for a learning based routing protocol

Content Provider	IEEE Xplore Digital Library
Author	Terzioglu, H. Kocak, T.
Copyright Year	2004
Description	Author affiliation: Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA (Terzioglu, H.; Kocak, T.)
Abstract	Recently, cognitive packet network (CPN) is proposed as an alternative to the IP based network architectures and shows similarity with the discrete active networks. In CPN, there is no routing table, instead reinforcement learning (random neural networks) is used to route packets. CPN routes packets based on QoS, using measurements that are constantly collected by packets and deposited in mailboxes at routers. The applicability of the CPN concept has been demonstrated through several software implementations. However, higher data traffic and increasing packet processing demands require the implementation of this new network architecture in hardware. In this paper, we present a network processor architecture, which supports this learning based protocol.
Starting Page	261
Ending Page	264
File Size	345984
Page Count	4
File Format	PDF
ISBN	0780383222
DOI	10.1109/NEWCAS.2004.1359081
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Active circuits Neural network architecture Learning systems
Content Type	Text
Resource Type	Article

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