NDLI: Formal verification of a bus structure modeled in SystemC

Content Provider	IEEE Xplore Digital Library
Author	Habibi, A. Tahar, S. Halleb, L.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada (Habibi, A.; Tahar, S.; Halleb, L.)
Abstract	In this paper, we present the formal verification of a bus structure modeled in SystemC. SystemC is an emerging system level design and verification language based on C++ object oriented paradigms. The verification approach is based on both abstract interpretation (for model reduction) followed by model checking of some of the bus properties. In the abstraction phase, we statically analyze the SystemC model considered as C++ code augmented by library constructors, components and entities. We also provide a graphical representation of the reduced model, suitable for debugging and verification purposes. We use the Cadence FormalCheck tool to verify designs properties on the abstracted (reduced) bus model translated into Verilog code. While the verification of the original model was not possible to perform, we succeeded in checking all properties on the reduced model.
Starting Page	61
Ending Page	64
File Size	316574
Page Count	4
File Format	PDF
ISBN	0780383222
DOI	10.1109/NEWCAS.2004.1359017
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Formal verification Object oriented modeling Hardware design languages Libraries System-level design Reduced order systems Debugging Electronic design automation and methodology Productivity Proposals
Content Type	Text
Resource Type	Article

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