NDLI: Impact of fin shape variability on device performance towards 10nm node

Content Provider	IEEE Xplore Digital Library
Author	Tomida, K. Hiraga, K. Dehan, M. Hellings, G. Jang, D. Miyaguhi, K. Chiarella, T. Kim, M. Mocuta, A. Horiguchi, N. Mercha, A. Verkest, D. Thean, A.
Copyright Year	2015
Description	Author affiliation: imec, Leuven, Belgium (Dehan, M.; Hellings, G.; Jang, D.; Miyaguhi, K.; Chiarella, T.; Kim, M.; Mocuta, A.; Horiguchi, N.; Mercha, A.; Verkest, D.; Thean, A.) \|\| SONY Corp., Atsugi, Japan (Tomida, K.; Hiraga, K.)
Abstract	A transition from planar to FinFET brings additional variability sources from 3D channel structure. In this study, the impact of fin shape variability on device performance, especially from the view point of short channel effect control, is investigated with using Si-validated TCAD. This reveals that the width, height and taper angle of fin have significant impact on the electrostatics of the device. In addition, through the statistical Monte-Carlo simulations with compact model, the impact of fin shape variability is visualized in comparison with conventional device variability sources, i.e., gate length, work function, and equivalent oxide thickness. As a result, fin width and fin angle are found to be major variability source in addition to gate length. This indicates that the suppression of the process variability in fin width and fin angle is key to control device variability, especially in advanced node.
Starting Page	1
Ending Page	4
File Size	876727
Page Count	4
File Format	PDF
ISBN	9781479976690
DOI	10.1109/ICICDT.2015.7165884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-01
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Shape FinFETs Market research Logic gates Silicon Electrostatics Performance evaluation Monte-Carlo FinFET variability 14nm 10nm short channel effect TCAD Compact Model
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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