NDLI: Assessment of SiGe quantum well transistors for DRAM peripheral applications

Content Provider	IEEE Xplore Digital Library
Author	Ritzenthaler, R. Schram, T. Eneman, G. Mocuta, A. Horiguchi, N. Thean, A.V.-Y. Spessot, A. Aoulaiche, M. Fazan, P. Noh, K.B. Son, Y.
Copyright Year	2015
Description	Author affiliation: Micron Technol. Belgium, Leuven, Belgium (Spessot, A.; Aoulaiche, M.; Fazan, P.) \|\| imec, Leuven, Belgium (Ritzenthaler, R.; Schram, T.; Eneman, G.; Mocuta, A.; Horiguchi, N.; Thean, A.V.-Y.)
Abstract	In this work, the potential of $Si_{1-x}Ge_{x}$ Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for $Si_{1-x}Ge_{x}$ Quantum Well devices, which is attributed to junction induced defects creation at the SiGe/Si buffer layer interface. This highlights the need for a dedicated junction solution in SiGe QW devices. The junction leakages are also investigated, and it is found that Band to Band Tunneling is the dominant mechanism setting the minimum Off-state leakage current. Band to Band Tunneling is increasing when the Ge content is increased, and it may effectively cap the allowed Ge channel content for Low Power Applications. The minimum Off state leakage requirement for DRAM peripheral applications is still obtained for a Ge concentration of 45%.
Starting Page	1
Ending Page	4
File Size	831982
Page Count	4
File Format	PDF
ISBN	9781479976690
DOI	10.1109/ICICDT.2015.7165875
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-01
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Random access memory Silicon germanium Transistors Silicon Junctions Tunneling SiGe channels DRAM DRAM periphery circuitry Junction leakage Low Power applications
Content Type	Text
Resource Type	Article

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