NDLI: Film properties and integration performance of carbon doped oxides

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2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

Welcome from the ICICDT Conference Chair

ICICDT Conference Committee

Challenges and opportunities in the semiconductor industry

Impact of process scaling on the efficacy of leakage reduction schemes

Leakage-induced signal degradation in VLSI interconnection for buffered bus line & logic

Statistical estimation of circuit timing vulnerability due to leakage-induced power grid voltage drop

Impact of process variation phenomena on performance and quality assessment

A 0.18 /spl mu/m 4 Mbit toggling MRAM

An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V

Performances of Si nanocrystal memories obtained by by CVD and their potentialities to further scaling of non-volatile memories

Prospects of emerging new memory technologies

PRAM process technology

Advanced device structure for aggressively scaled MOSFETs

Advanced transistor structures for high performance microprocessors

Physics-based device models for nanoscale double-gate MOSFETs

Highly performant double gate MOSFET realized with SON process: how we address the design and process for the GAA SON challenges ?

Flexible threshold voltage 4-terminal FinFETs

Multi gated device architectures advances, advantages and challenges

Advanced double-gate fully-depleted silicon-on-insulator (DG-FDSOI) device and device impact on circuit design & power management

Advanced SOI substrate manufacturing

Investigation of nano interconnects for an early experimental assessment of future interconnect challenges

Film properties and integration performance of carbon doped oxides

A study of SiN cap NH/sub 3/ plasma pre-treatment process on the PID, EM, GOI performance and BEOL defectivity in Cu dual damascene technology

Plasma damage considerations involving metal-insulator-metal (MIM) capacitors

SOI charging prevention: chip-level net tracing and diode protection

Monitoring and preventing arc-induced wafer damage in 300mm manufacturing

The double-gate FinFET: device and impact on IC design automation

Design and implementation of the POWER5/spl trade/ microprocessor

Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

Recent developments in high-performance system-on-chip IC design

Minimizing power under performance constraint

Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic

Statistical design for variation tolerance: key to continued Moore's law

Design aspects of a 4 Mbit 0.18 /spl mu/m 1T1MTJ toggle MRAM memory

Maximum clock frequency distribution model with practical VLSI design considerations

Analog front-end and power management integration on a 0.13 /spl mu/m CMOS ADSL SoC

Cell library techniques using advanced transistor structures

Build-in reliability analysis for circuit design in the nanometer technology era

Advanced flash memory reliability

The development of dual gate poly scheme with plasma nitrided gate oxide for mobile high performance DRAMs: plasma process monitoring and the correlation with electrical results

Plasma damage in HIMOS/spl trade/ non-volatile memories (NVM)

Analysis of plasma damage on phase change memory cells

ONO charging at different stages of microFlash/sup /spl reg// process flow

Integration challenges of new materials and device architectures for IC applications

Advanced germanium MOSFET technologies with high-/spl kappa/ gate dielectrics and shallow junctions

Impact of elevated oxygen concentration on in-situ doped sub-50 nm SiGe and SiGeC base strained layer NPN HBT

Threshold voltage instability and plasma induced damage of polySi/HfO/sub 2/ devices - positive impact of deuterium incorporation

Strained silicon: engineered substrates and device integration

Atomic layer deposition of high-k thin films for gate and capacitor dielectrics

Trends in gate stack engineering

Electrical performance improvement in SiO/sub 2//HfSiO high-k gate stack for advanced low power device application

Heavy ion irradiation of floating gate memory cells

Reducing FHDP plasma induced damage with silicon-rich oxide and oxynitride barrier layers

Low-K cu damascene interconnection leakage and process induced damage assessment

Atomic scale defects in the Si/SiON system and the negative bias temperature instability

Effect of channel width, length, and latent damage on NBTI

Energy dependence of vacuum-ultraviolet-induced radiation damage to electronic materials

Atmospheric neutron effects in advanced microelectronics, standards and applications

Radiation assurance for the space environment

Monte-Carlo simulation of the effects of vacuum ultraviolet radiation on electronic materials

Time evolution of V/sub TH/ distribution under BT stress in ultra-thin gate oxides

Can TDDB continue to serve as reliability test method for advance gate dielectric?

Thin oxide degradation from HDP-CVD oxide deposition in 300mm process

Breakdown transients in ultra-thin gate oxynitrides

Optimization and scaling limit forecast of nitrided gate oxide using an equivalent nitride/oxide (N/O) stack model

Film properties and integration performance of carbon doped oxides

Content Provider	IEEE Xplore Digital Library
Author	M'Saad, H.
Copyright Year	2004
Description	Author affiliation: Appl. Mater. Inc., Santa Clara, CA, USA (M'Saad, H.)
Abstract	Summary form only given. The semiconductor industry has witnessed a successful introduction of copper based interconnects and low permittivity insulators with 130nm node devices. The advent of 90nm node devices has led to the introduction of first generation of carbon doped dielectric films. Further scaling will require materials with lower permittivity and this has accelerated the development of a second generation of carbon doped oxides with imbedded porosity. While the addition of carbon to a silicon based dielectric lowers the permittivity of the insulator, carbon doping may also lead to degradation in the surface properties of such films. Frequently, carbon enrichment at surfaces is known to cause issues with the wetting characteristics of the surface. In addition, the mechanical strength of interfaces formed with carbon enriched surfaces may be poor compared to congruent surfaces. The high number of chemically and morphologically different materials in the integrated interconnects structure increase the possibility of mechanical structural failure. A detailed understanding of the basic material properties and the behavior of the carbon doped materials during subsequent processing is therefore of prime importance. This paper will present an overview of process and film property characterization of different generations of carbon doped oxides. Integration properties of these films and correlation to processing parameters and physical properties of the materials will be discussed. Novel processing techniques are discussed that enable the implementation of advanced low dielectric constant materials without sacrificing the high volume manufacturability of such films.
Sponsorship	IEEE Central Texas Sect. Japan Soc. Appl. Phys
File Size	42192
File Format	PDF
ISBN	0780385284
DOI	10.1109/ICICDT.2004.1309922
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surface morphology Permittivity Dielectric materials Semiconductor films Dielectrics and electrical insulation Organic materials Electronics industry Copper Dielectric films Semiconductor materials
Content Type	Text
Resource Type	Article

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