NDLI: A 0.18 /spl mu/m 4 Mbit toggling MRAM

Content Provider	IEEE Xplore Digital Library
Author	Durlam, M. Addie, D. Akerman, J. Butcher, B. Brown, P. Chan, J. DeHerrera, M. Engel, B.N. Feil, B. Grynkewich, G. Janesky, J. Johnson, M. Kyler, K. Molla, J. Martin, J. Nagel, K. Nahas, J. Ren, J. Rizzo, N.D. Rodriguez, T. Savtchenko, L. Salter, J. Slaughter, J.M. Smith, K. Sun, J.J. Lien, M. Papworth, K. Shah, P. Qin, W. Williams, R. Wise, L. Tehrani, S.
Copyright Year	2004
Description	Author affiliation: Semicond. Products Sector, Motorola Inc., Chandler, AZ, USA (Durlam, M.; Addie, D.; Akerman, J.; Butcher, B.; Brown, P.; Chan, J.; DeHerrera, M.; Engel, B.N.; Feil, B.; Grynkewich, G.; Janesky, J.; Johnson, M.; Kyler, K.; Molla, J.; Martin, J.; Nagel, K.)
Abstract	A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.
Sponsorship	IEEE Central Texas Sect. Japan Soc. Appl. Phys
Starting Page	27
Ending Page	30
File Size	334916
Page Count	4
File Format	PDF
ISBN	0780385284
DOI	10.1109/ICICDT.2004.1309899
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic tunneling Magnetic separation Magnetic switching Electric resistance Energy barrier CMOS process Electrodes Delay Electrons Polarization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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