NDLI: A Reed-Solomon Algorithm for FPGA Area Optimization in Space Applications

Content Provider	IEEE Xplore Digital Library
Author	Almeida, G.M. Bezerra, E.A. Cargnini, L.V. Fagundes, R.D.R. Mesquita, D.G.
Copyright Year	2007
Description	Author affiliation: PUCRS, Porto Alegre (Almeida, G.M.; Bezerra, E.A.; Cargnini, L.V.; Fagundes, R.D.R.)
Abstract	This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller components allow for better system adaptation, which is an expected feature of reconfigurable systems for space applications. The approach is applied in the design stage of a component for the communications module of an on-board computer system. The chosen component is a Reed-Solomon encoder, which has been implemented using a Hardware Description Language (VHDL) according to CCSDS recommendations, and targeting an FPGA platform. The paper investigates traditional alternatives for the encoder implementation, introduces the algebraic theory behind the proposed approach, describes the design process and discusses the area figures reached by the new design.
Starting Page	243
Ending Page	249
File Size	438435
Page Count	7
File Format	PDF
ISBN	9780769528663
DOI	10.1109/AHS.2007.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-05
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reed-Solomon codes Field programmable gate arrays Space technology Hardware Space missions Communication systems Design optimization Application software Algorithm design and analysis Random access memory
Content Type	Text
Resource Type	Article

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