NDLI: Effect of interlayer trapping and detrapping on the determination of interface state densities on high-k dielectric stacks

Content Provider	IEEE Xplore Digital Library
Author	Dueas, S. Castan, H. Garcia, H. Gomez, A. Bailon, L. Toledano-Luque, M. del Prado, A. Martil, I. Gonzalez-Diaz, G.
Copyright Year	2009
Description	Author affiliation: Departamento de Electricidad y Electrónica, E.T.S.I. Telecomunicación, Universidad de Valladolid, Campus "Miguel Delibes", 47011 Valladolid, Spain. E-mail: sduenas@ele.uva.cs; Departamento de Fisica Aplicada III Electricidad y Electrónica), Facultad de Ciencias Físicas, Universidad Complutense, 28040 Madrid, Spain (Dueas, S.) \|\| Departamento de Electricidad y Electrónica, E.T.S.I. Telecomunicación, Universidad de Valladolid, Campus "Miguel Delibes", 47011 Valladolid, Spain.; Departamento de Fisica Aplicada III Electricidad y Electrónica), Facultad de Ciencias Físicas, Universidad Complutense, 28040 Madrid, Spain (Castan, H.; Garcia, H.; Gomez, A.; Bailon, L.; Toledano-Luque, M.; del Prado, A.; Martil, I.; Gonzalez-Diaz, G.)
Abstract	Al/HfO/SiNx:H/n-Si metal-insulator-semiconductor (MIS) capacitors have been studied by electrical characterization. Films of silicon nitride were directly grown on n-type silicon substrates by electron-cyclotron-resonance assisted chemical-vapor-deposition (ECR-CVD). Silicon nitride thickness was varied from 2.96 to 6.64 nm. Afterwards, 12 nm thick hafnium oxide films were deposited by the high-pressure reactive sputtering (HPS) approach. Interface state densities were determined by deep-level transient spectroscopy and simultaneous high and low frequency capacitance-voltage (HLCV). The simultaneous measurements of the high and low frequency capacitance voltage provide interface trap density values in the range of $10^{11}$ $cm^{-2}eV^{-1}$ for all the samples. However, a significant increase of this density of about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride interfacial layers. In this work we probe that this increase is an artifact that must be attributed to traps existing at the HfO: H interlayer interface. These traps are more easily charged or discharged as this interface comes near the substrate, that is, as thinner the SiN:H interface layer. The trapping/detrapping mechanisms increase the capacitance transient and, in consequence, the DLTS measurements have contributions not only from the insulator/substrate interface but also from the HfO:H interlayer interface.
Starting Page	1
Ending Page	4
File Size	4583236
Page Count	4
File Format	PDF
ISBN	9781424428380
DOI	10.1109/SCED.2009.4800414
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-11
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interface states High-K gate dielectrics Hafnium oxide Silicon compounds Frequency Capacitance-voltage characteristics Capacitance measurement Electron traps Metal-insulator structures Capacitors
Content Type	Text
Resource Type	Article

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