NDLI: A low cost, low power AES ASIC with high DPA resisting ability

Content Provider	IEEE Xplore Digital Library
Author	Bo Yu Xiangyu Li Naiwen Zhang Yihe Sun
Copyright Year	2009
Description	Author affiliation: Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China (Bo Yu; Xiangyu Li; Naiwen Zhang; Yihe Sun)
Abstract	THUAES06 that implements the standard AES algorithm is characterized by low cost, low power and high differential power analysis (DPA) resisting ability enhancement. The DPA resisting ability enhancement is achieved by using fine grained shuffling as the DPA countermeasure of the main part and implementing vulnerable function unit with dual rail asynchronous circuits. THUAES06 is implemented in SMIC 0.18 μm technology. Its average energy of encrypting or decrypting one 128 bits plaintext or cipher text is 19nJ if initial key need not be changed. Its core area is $0.43mm^{2}.$ The power traces needed to disclose the secrete keys are more than 33,000.
Starting Page	285
Ending Page	288
File Size	1026206
Page Count	4
File Format	PDF
ISBN	9781424444335
DOI	10.1109/ASSCC.2009.5357254
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-16
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Application specific integrated circuits Cryptography Energy consumption Information analysis Arithmetic Random number generation Kernel Solid state circuits Sun
Content Type	Text
Resource Type	Article

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