NDLI: 10 GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13µm CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Sheng-Chuan Liang Ding-Jyun Huang Chen-Kang Ho Hao-Chiao Hong
Copyright Year	2007
Description	Author affiliation: Nat. Chiao Tung Univ. Hsinchu, Hsinchu (Sheng-Chuan Liang; Ding-Jyun Huang; Chen-Kang Ho; Hao-Chiao Hong)
Abstract	This paper demonstrates a 10 GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design of advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2 V supply. The areas of the ADC and DAC are 0.1575 $mm^{2}$ and 0.0636 $mm^{2},$ respectively in 0.13 mum CMOS technology.
Starting Page	416
Ending Page	419
File Size	326495
Page Count	4
File Format	PDF
ISBN	9781424413591
DOI	10.1109/ASSCC.2007.4425719
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-12
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Analog-digital conversion Digital-analog conversion Transceivers Logic gates CMOS logic circuits Feedback amplifiers Sampling methods Semiconductor device measurement Dynamic range
Content Type	Text
Resource Type	Article

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