NDLI: Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications

Content Provider	IEEE Xplore Digital Library
Author	Kuan-Hung Chen Kuo-Chuan Chao Jinn-Shyan Wang Yuan-Sun Chu Jiun-In Guo
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi (Kuan-Hung Chen; Kuo-Chuan Chao; Jinn-Shyan Wang; Yuan-Sun Chu)
Abstract	This paper presents the design exploration and application of a technique to suppress the spurious power dissipation existed in the data-paths for multimedia VLSI designs. The proposed technique adopts the design concept of separating the arithmetic units into most significant part (MSP) and least significant part (LSP), and then freezing the MSP whenever this part of circuits does not affect the computation result. This paper first explores three implementation approaches of realizing the SPST-based design concept to decide the most efficient one, and then uses this approach to reduce the spurious power of the multi-transform coding design in H.264 systems. The post-layout simulations show that the proposed SPST can save average 27.38% of power dissipation of the multi-transform design
Sponsorship	IEEE SSC
Starting Page	341
Ending Page	344
File Size	574119
Page Count	4
File Format	PDF
ISBN	0780391624
DOI	10.1109/ASSCC.2005.251735
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-01
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Circuits Transform coding Adders Energy consumption Very large scale integration Data analysis Chaos Arithmetic Computational modeling transform coding H.264 power optimization
Content Type	Text
Resource Type	Article

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