NDLI: A single-chip direct-sequence spread-spectrum CMOS transceiver for high performance, low cost 2.4-GHz cordless applications

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2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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2005 IEEE Asian Solid-State Circuits Conference

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Table of contents

Design and Technology Collaboration

T-Engine The Open Platform for the Ubiquitous Computing Age

Memory Technologies for Mobile Era

A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application

A 16M SRAM with improved characteristics using DRAM technology

The Power Conscious Synergistic Processor Element of a Cell Processor

A Wireless LAN Baseband LSI for High-Definition A/V Content Transmission

A Vernier Over Sampling and Alignment technique for Gb/s Serial Communication

A Wide Band CDR for Digital Video Data Transmission

A Sub-1V CMOS 2.5Gb/s Serial Link Transceiver Using 2X Oversampling

3.3/5V Multi-rate Laser Diode Driver and Limiting Amplifier for Optical Transceivers

A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays

A 667MT/s 10.7GB/s Multiprocessor Bus Interface

A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM

A Self-Calibrate All-Digital 3Gbps SATA Driver Design

A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration

Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST

Practical Synthesis of 13-bit 40-MSample/s Pipelined ADC

An Outside-Rail Opamp Design Targeting for Future Scaled Transistors

Sampled-and-Hold Based Automatic Calibration Modulator for WLAN Transmitter

Low Power 0.18 μm CMOS Dual-Band Front-End

A 142dB Dynamic Range CMOS Image Sensor with Multiple Exposure Time Signals

A Large-Displacement CMOS-Micromachined Thermal Actuator with Capacitive Position Sensing

A monolithic control circuit for a 1cm3 microrobot for biological experiments

Realization of Trans-impedance Amplifier for Particle Counting Chip

On-Chip Voice-Coil Motor Driver for Mobile Auto-Focus Camera Applications

Initial-On ESD Protection Design with PMOS-Triggered SCR Device

SRAM Circuit with Expanded Operating Margin and Reduced Stand-by Leakage Current Using Thin-BOX FD-SOI Transistors

A Low Power 128Mb Pseudo SRAM Using Hyper Destructive Read Architecture

A 75MHz MRAM with Pipe-Lined Self-Reference Read Scheme for Mobile/Robotics Memory System

An Internal Voltage Generation System of Flash Memory Module Embedded in a Microcontroller

An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory

A 0.1-25.5-GHz Differential Cascaded-Distributed Amplifier in 0.18- μm CMOS Technology

Low Power 60 dB Gain Range with 0.25 dB Resolution CMOS RF Programmable Gain Amplifier for Dual-band DAB/T-DMB Tuner IC

A Fully Integrated CMOS RF Power Amplifier with Parallel Power Combining and Power Control

A 1.0-V 15.6-dBm 39.5%-PAE CMOS Class-E Power Amplifier with On-Chip Transformer for Q Enhancement

VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time

95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping

A Fast Settling Low Dropout Linear Regulator with Single Miller Compensation Capacitor

On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes

A Dual-Phase Digital PWM Controller for DC-DC Switching Converters with Current Balancing

Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise

A 5Gbps CMOS Automatic Gain Control Amplifier for 10GBase-LX

A CMOS Gm-C Analog Pre-Equalizer for 1000BASE-T Analog Receive Filters

A 90 dBΩ, 10 Gbps Optical Receiver in a 0.18 μm CMOS Technology

A Wideband CMOS Variable-Gain Low-Noise Amplifier for Cable TV Tuners

Noise Reduction in LNAs Using a Conductive Path to Ground Technique in SiGe Technology

4/2 PAM Pre-emphasis Transmitter with Combined Driver and Mux

A Wideband 0.18-μm CMOS ΔΣ Fractional-N Frequency Synthesizer with a single VCO for DVB-T

A Fast-Switching Frequency Synthesizer for UWB Applications

A Multimode GSM/DCS/WCDMA Double Loop Frequency Synthesizer

A 40-GHz Distributed-Load Static Frequency Divider

Ultra-Low-Voltage CMOS Static Frequency Divider

A 10-GHz CMOS PLL with an Agile VCO Calibration

A Low Power Digital IC Design Inside the Wireless Endoscopy Capsule

A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems

A MRMDF FFT Processor for MIMO OFDM Applications

Universal Architectures for Reed-Solomon Error-and-Erasure Decoder

Energy-Efficient Optimization of the Viterbi ACS Unit Architecture

A 1.1-Gb/s 4092-bit Low-Density Parity-Check Decoder

A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication

A 4.0-mW 2-Mbps Programmable BFSK Transmitter For Capsule Endoscope Applications

A Fully-Integrated Direct Conversion Receiver for CDMA and GPS applications

A single-chip direct-sequence spread-spectrum CMOS transceiver for high performance, low cost 2.4-GHz cordless applications

A Complete Dual-band Chip-set with USB 2.0 Interface for IEEE 802.11 a/b/g WLAN applications

A Single-Chip Dual-Band 0.25μm CMOS Transceiver for 802.11a/b/g Wireless LAN

A 1.3-2.8 GHz Wide Range CMOS LC-VCO Using Variable Inductor

Low-Phase Noise LC-tank Quadrature Voltage Controlled Oscillator

A 1V Dual-Band VCO Using an Integrated Variable Inductor

A CMOS VCO with Optimized Tune Branches for Zero-IF CDMA Cellular Application in a 0.5μm BiCMOS process

A Low-Phase-Noise Low-Phase-Error 2.4GHz CMOS Quadrature VCO

A Wide Lock-in Range PLL using Self-Calibrating Technique for Processors

All-Digital PLL with Ultra Fast Acquisition

A Calibrated Pulse Generator for Impuljse-radio UWB Applications

A 1.2Mpixels/s/mW 3-D Rendering Processor For Portable Multimedia Application

An 865-μW H.264/AVC Video Decoder for Mobile Applications

A 231MHz, 2.18mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3D Graphics System

Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme

An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design

Mismatch Modeling and Simulation Methodology for Predicting the Output Voltage Variation of an LCD Driver

A 5.25 GHz Even Harmonic Mixer for Low Voltage Direct Conversion Receivers

A Wide-band Low Noise Quadrature CMOS VCO

A Personal-Use Single-Chip Emulator Using Dynamically Reconfigurable Logic Array

Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique

A Single-Chip Low-Power Tunable CMOS Low-IF Single-Conversion ISM Receiver

Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications

A 0.9mW 0.01-1.4GHz Wideband CMOS Low Noise Amplifier for Low-Band Ultra Wideband Applications

A 900 MHz CMOS RF Direct Conversion Receiver Front-end with 3-dB NF and 30-KHz 1/f Noise Corner

Single Polysilicon Gate High-Density Logic Using Independently-Controlled Double-Gate Devices

A 900 MHz Low Voltage Low Power Variable Gain CMOS Transmitter Front-end

A High Efficiency ALL-PMOS Charge Pump for Low-Voltage Operations

A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

A Fast Offset-cancellation Single-to-differential Stage for Burst-mode Receiver Design

A 0.5 V 3.1 mW Fully Monolithic OOK Receiver for Wireless Local Area Sensor Network

Digitally controlled phase locked loop with tracking analog-to-digital converter

A 1.8-V 40-mW Wide-Band CMOS Synthesizer for Cable Tuner Applications

Dual-Bias Power Amplifier Designs for WLAN Applications

A 1.25 to 5Gbps LVDS Transmitter with a Novel Multi-Phase Tree-Type Multiplexer

Global High-Speed Signaling in Nanometer CMOS

A Low-Power Dual-Band WLAN CMOS Receiver

A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

DSP Architecture with Jumping-Floating-Point Number System

A Low-phase-noise 1-GHz LC VCO Differentially Tuned by Switched Step Capacitors

Novel Test Structure to emulate Capacitance Variations of a Rate-Grade MEMS Gyroscope

4 Gbps On-Chip Interconnection using Differential Transmission Line

Design of a Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate

SiGe HBT based 24-GHz LNA and VCO for Short-Range Ultra-Wideband Radar Systems

Audio-Specific Signal Processor(ASSP) for High-Quality Audio Codec

A CMOS vision sensor with on-the-fly histogram equalization using TFS encoding and AER read-out

A 1-V 27mW 10-GHz LC-NOR-Ring QVCO for UWB-OFDM Direct Frequency Synthesizer

Quadrature Oscillator with Negative-Resistance Compensated Transformer Couple

A 35MS/s and 2V/2.5V Current-mode Sample-and-Hold Circuit with an Input Current Linearization Technique

A Direct Conversion CMOS Front-End for 2.4 GHz Band of IEEE 802.15.4 Standard

Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis

A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit

A CMOS Image Rejection Mixer for DAB/DMB Low-IF Tuner IC Exhibiting 41dB Adjacent Channel Rejection Ratio

A 40~900MHz Broadband CMOS Differential LNA with Gain-Control for DTV RF Tuner

A 2.4~6GHz CMOS Broadband High-Gain Differential LNA for UWB and WLAN Receiver

A Low-Power and Compact Analog CMOS Processing Chip for Portable ECG Recorders

On-demand Pipelining for Improving Energy-Awareness

Design of a High-Performance Switch for Circuit-Switched On-Chip Networks

Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms

A 1.1-V 9.9-mW MC-CDMA Downlink Baseband Receiver IC for Next-Generation Cellular Communication Systems

A 2.4GHz CMOS Quadrature VCO for 2.4GHz WLAN/Bluetooth Applications

A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors

A 1.8-V 531-mW Single-Chip Single-Conversion CMOS Cable TV Tuner

10GBase-LX CMOS Automatic Gain Control Amplifier Design

FPGA Prototype for WLAN OFDM Baseband with STPE of I/Q Mismatch Self Calibration Algorithm

Scalable Security Processor Design and Its Implementation

Area Efficient Architecture for the Embedded Block Coding in JPEG 2000

A Wideband Programmable Spread-Spectrum Clock Generator

The Split-Path AND-type Match-line Scheme for Very High-Speed Content Addressable Memories

720 × 480 30fps Efficient Prediction Core Chip for Stereo Video Hybrid Coding System

Ultra Low-Cost 3.2Gb/s Optical-Rate Reed Solomon Decoder IC Design

Evening Panel Discussion

Conference committee

A single-chip direct-sequence spread-spectrum CMOS transceiver for high performance, low cost 2.4-GHz cordless applications

Content Provider	IEEE Xplore Digital Library
Author	Ying-His Lin Ka-Un Chan Chia-Jun Chang Tsung-Ming Chen Ying-Yao Lin Han-Chang Kang Ren-Chieh Liu Ning-You Yan
Copyright Year	2005
Description	Author affiliation: Realtek Semicond. Corp., Hsinchu (Ying-His Lin; Ka-Un Chan; Chia-Jun Chang; Tsung-Ming Chen; Ying-Yao Lin; Han-Chang Kang)
Abstract	A fully-integrated direct-sequence spread-spectrum (DSSS) CMOS transceiver for 2.4-GHz ISM band is presented. It integrates a RF transceiver, a frequency synthesizer, baseband filters, digital signal processing, an adaptive differential pulse-code modulation (ADPCM) codec, and a programmable PA pre-driver. The transceiver chip achieves a measured sensitivity of -103 dBm and an output power of 3 dBm. The total chip area is 3.4 times 3.3 $mm^{2}$ in a standard RF 0.18-mum CMOS technology
Sponsorship	IEEE SSC
Starting Page	253
Ending Page	256
File Size	512060
Page Count	4
File Format	PDF
ISBN	0780391624
DOI	10.1109/ASSCC.2005.251713
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-01
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Spread spectrum communication Transceivers Costs Radio frequency Pulse modulation CMOS technology Frequency synthesizers Baseband Adaptive filters Digital filters
Content Type	Text
Resource Type	Article

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