NDLI: Efficient test and repair architectures for 3D TSV-based random access memories

Content Provider	IEEE Xplore Digital Library
Author	Shyue-Kung Lu Uang-Chang Lu Seng-Wen Pong Hao-Cheng Cheng
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan (Shyue-Kung Lu; Uang-Chang Lu; Seng-Wen Pong; Hao-Cheng Cheng)
Abstract	In this paper, we propose a test and repair architecture for 3D ICs consisting of stacked memory dies (slave dies) and a processor die (master die). The proposed architecture supports known-good-die (KGD) test, known-good-stack (KGS) test, and final test and repair. However, instead of incorporating spare elements in each memory die, a small-size redundant memory is incorporated into the processor die. That is, the added redundancy can be used globally for repairing faulty cells among all other stacked memory dies. Each slave die contains the BIST and BIRA modules for performing KGD and KGS tests and redundancy analysis. The results of redundancy analysis then can be used for die stacking, yield management, and BISR (built-in self-repair) after the final test. An 1149.1-based test interface is added for each slave die and only four test pads are required for test and repair purposes. Based on the results of the BIRA module, a simple matching algorithm is proposed to increase the stacking yield. According to experimental results, the hardware overhead for an 8K × 32-bit SRAM is only 2.6%. Moreover, the stacking yield can be improved significantly.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	4
File Size	652176
Page Count	4
File Format	PDF
ISBN	9781467344357
e-ISBN	9781467344364
DOI	10.1109/VLDI-DAT.2013.6533889
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stacking Redundancy Maintenance engineering Three-dimensional displays Built-in self-test Circuit faults Random access memory
Content Type	Text
Resource Type	Article

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