NDLI: A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance

Content Provider	IEEE Xplore Digital Library
Author	Ching-Che Chung Chang-Jun Li
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan (Ching-Che Chung; Chang-Jun Li)
Abstract	In this paper, a low-power delay-recycled all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC corrects the duty-cycle of the distorted clock to 50% under process, voltage, and temperature (PVT) variations. Besides, the delay-recycled architecture reduces the required length of the delay line to 1/2 of the input clock period. The proposed ADDCC architecture saves both the chip area and the power consumption. In addition, the proposed ADDCC can work properly at unbalanced process corners (i.e. SF and FS). The proposed design is implemented in a standard performance 90nm CMOS process, and the active area is 70 μm × 70 μm. The simulation results show that the maximum duty cycle error of the output clock can be less than 1.9% with the input duty-cycle ranging from 20% to 80 %, and the input frequency ranging from 450 MHz to 1 GHz. The power consumption of the proposed ADDCC is 1.7mW at 450MHz and 3.45mW at 1 GHz with a 1.0V power supply.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	4
File Size	709588
Page Count	4
File Format	PDF
ISBN	9781467344357
e-ISBN	9781467344364
DOI	10.1109/VLDI-DAT.2013.6533869
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Delay lines Power demand Computer architecture System-on-chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A low-power delayrecycled all-digital duty-cycle corrector with unbalanced process variations tolerance (2013)

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

A Wide-Range All-Digital Duty Cycle Corrector with a Period Monitor

All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

Low-power on-chip bus architecture using dynamic relative delays

A range extending delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

An output tracking delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance

Similar Documents

A low-power delayrecycled all-digital duty-cycle corrector with unbalanced process variations tolerance (2013)

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

A Wide-Range All-Digital Duty Cycle Corrector with a Period Monitor

All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture

Low-power on-chip bus architecture using dynamic relative delays

A range extending delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

An output tracking delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance