NDLI: Sensorless dead-time exploration for digitally controlled switching converters

Content Provider	IEEE Xplore Digital Library
Author	Bo-Ting Yeh Chun-Hung Yang Kai-Cheung Juang Chien-Hung Tsai
Copyright Year	2013
Description	Author affiliation: ICL, ITRI, Hsinchu, Taiwan (Bo-Ting Yeh; Kai-Cheung Juang) \|\| Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Chun-Hung Yang; Chien-Hung Tsai)
Abstract	This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	4
File Size	822025
Page Count	4
File Format	PDF
ISBN	9781467344357
e-ISBN	9781467344364
DOI	10.1109/VLDI-DAT.2013.6533802
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Quantization (signal) Clocks DC-DC power converters MOSFET Logic gates digital control DC-DC converter dead-time
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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