NDLI: Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array

Content Provider	IEEE Xplore Digital Library
Author	Ming-Chien Tsai Yi-Wei Lin Hao-I Yang Ming-Hsien Tu Wei-Chiang Shih Nan-Chun Lien Kuen-Di Lee Shyh-Jye Jou Ching-Te Chuang Wei Hwang
Copyright Year	2012
Description	Author affiliation: Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C. (Ming-Chien Tsai; Yi-Wei Lin; Hao-I Yang; Ming-Hsien Tu; Nan-Chun Lien; Shyh-Jye Jou; Ching-Te Chuang; Wei Hwang) \|\| Faraday Technology Corporation, Hsinchu, Taiwan, R.O.C. (Wei-Chiang Shih; Kuen-Di Lee)
Abstract	One of the major reliability concerns in nano-scale CMOS VLSI design is the time-dependent Bias Temperature Instability (BTI) degradation. Negative Bias Temperature Instability and Positive Bias Temperature Instability (NBTI and PBTI) weaken MOSFETs over usage/stress time. We present an embedded 6T SRAM ring oscillator structure which provides in-situ measurement/characterization capability of cell transistor degradation induced by bias temperature instability. The viability of the embedded ring oscillator odometer and the impact of bias temperature instability are demonstrated in 55nm standard performance CMOS technology.
Starting Page	1
Ending Page	4
File Size	516283
Page Count	4
File Format	PDF
ISBN	9781457720802
e-ISBN	9781457720819
DOI	10.1109/VLSI-DAT.2012.6212587
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-23
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Random access memory Degradation Ring oscillators Frequency measurement Arrays Reliability
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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