NDLI: Modeling multi-output filtering effects in PCMOS

Content Provider	IEEE Xplore Digital Library
Author	Singh, A. Basu, A. Ling, K. Mooney, V.J.
Copyright Year	2011
Description	Author affiliation: International Institute of Information Technology, Hyderabad, India (Singh, A.) \|\| School of EEE, Nanyang Technological University (NTU), Singapore (Basu, A.; Ling, K.; Mooney, V.J.)
Abstract	A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It requires characterization of unique probabilistic blocks to predict the error rates of a multi-block cascade structure. While the technique was shown to work for a probabilistic carry-select adder [4, 5], the technique needs a new model to work in a Wallace Tree Multiplier (WTM) where error propagates not only along the carry bit but also along the sum bit of the basic full adder building block utilized. In this paper we present a new model for characterization of probabilistic circuits/blocks and present a procedure to find and characterize unique circuits/blocks. Unlike prior approaches, our new model distinguishes distinct filtering effects per output. We apply the proposed model to a WTM and show that using our model, the methodology using a cascade structure [4] can predict WTM error-rates with reasonable accuracy in PCMOS.
Starting Page	1
Ending Page	4
File Size	324542
Page Count	4
File Format	PDF
ISBN	9781424485000
e-ISBN	9781424484997
DOI	10.1109/VDAT.2011.5783561
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-25
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit modeling Probabilistic logic Predictive models Mathematical model Error analysis Filtering Noise
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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